Posted by Colin Warwick
Hi, I’m Colin Warwick, High Speed Digital Design Flow Manager with the Agilent EEsof EDA high speed digital (formerly signal integrity) design flow group. This blog is about tips, tricks, and tutorial to help ensure signal integrity on high speed digital chip-to-chip data links.
Here’s my bio, which I wrote in the third person:
Colin Warwick is high speed digital product manager at Agilent EEsof EDA, where he is focused on multigigabit per second design and analysis tools. Prior to joining Agilent, Colin was with Royal Signals and Radar Establishment in Malvern, England, Bell Labs in Holmdel, NJ, and The MathWorks in Natick, MA. He completed his bachelor, masters, and doctorate degrees in physics at the University of Oxford, England. He has published over 50 technical articles and holds thirteen patents.
Thanks for visiting! Please see my blogroll below for other useful sites.
- DesignCon Community
- EEWeb Electronics Forum
- John Baprawski’s blog
- Bert Simonovich’s blog "Design Notes: Innovative Signal Integrity & Backplane Solutions"
- Eric Bogatin’s blog "What I Learned This Month"
- István Novák’s Electrical Integrity site
- Joe Civello’s RF Design Tips blog
- John Busco’s Semi-Blog
- My other blog: Wizards of Electromagnetism at Chip Design Magazine
- Paul Rako’s Anablog at EDN
- Rick Merritt’s Interconnects blog at EE Times
- SI-List E-mail Reflector
- Subscribe to EDN Magazine