Signal Integrity

On High Speed Digital Chip-to-Chip Links

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Posted by Colin Warwick

Hi, I’m Colin Warwick, High Speed Digital Design Flow Manager with the Agilent EEsof EDA high speed digital (formerly signal integrity) design flow group. This blog is about tips, tricks, and tutorial to help ensure signal integrity on high speed digital chip-to-chip data links.

Colin Warwick

A while ago I put in a redirect from the old domain signal-integrity-tips.com to our new home signal-integrity.tm.agilent.com. Please let me know at colin underscore warwick at agilent daht calm if anything is broken. For either one, our Privacy Policy and Terms of Service are the same as Agilent.com.

Thanks for visiting! Please see my blogroll below for other useful sites.
– Colin

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