In his retrospective Life of SPICE, Larry Nagel the co-author of SPICE (an acronym for "Simulation Program with Integrated Circuit Emphasis") noted:
SPICE was announced to the world … in Waterloo, Canada at the Sixteenth Midwest Symposium on Circuit Theory on April 12, 1973. The paper was presented by none other than Professor Donald O. Pederson of the University of California, Berkeley. I don’t think anyone had a clue of the impact of that paper or the computer program it described.
Well, impact it certainly had. So, in honor of SPICE’s thirty-sixth "birthday", here is the first of several interactive posts about how SPICE works. Here in part one we start simply with one time step (i.e. DC) solution of a circuit that consists of two unknown node voltages, V1, V2, a ground node V0, three known ohmic conductances, Gxy = 1/Rxy (where Ixy = Gxy (Vy – Vx) and x and y are the node indices), and three known current sources.
You can solve a circuit using either Kirchhoff’s current law or voltage law or both. These laws are named after a German physicist Gustav Robert Kirchhoff (1824-87). (The ch in Kirchhoff is pronounced like the ch in the Scots word loch.) SPICE is a modified nodal solver and uses the current law: the sum of the currents into each node is zero. We’ll talk about what the ‘modified’ bit means in a future posting on ’super nodes.’ We’ll also postpone a discussion about when Kirchhoff’s laws break down for a future post (hint: Faraday’s law trumps Kirchoff’s law).
The nodes are joined by branches, so the other ingredients are the branch constitutive equations of the components that join them, for example V = IR if it’s an ohmic resisitor, V = L dI/dt for an inductor, etc. In this simple example, we have three simultaneous equations, one each from node 0, 1, and 2:
… with three unknowns, V0, V1, and V2.
The same equations can be rearranged into matrix form, in this case the augmented (or indefinite) node conductance matrix relates the voltage and current vectors:
Note the ‘pattern of four’ that each conductance (e.g. G01 highlighted in yellow above) impresses into the conductance matrix:
In SPICE parlance, making this ‘pattern of four’ impression is called ’stamping the matrix.’ Conveniently, this ’stamping’ generalizes for any number of nodes and two terminal components. In a future post, we’ll show how a small modification to this method allows us to ’stamp in’ a three- or four-terminal component like a voltage-controlled current source (and hence deal with transistors).
Pairs of nodes with no physical branch element connecting them have a conductance of 0. In practical circuits, the average number of non-zero conductances per node is only ~3-4, whereas the number of nodes can be quite large: hundreds, thousands, even millions. Thus, practical circuits have sparse, not full, conductance matrices: SPICE can make use of the efficiency of a sparse matrix solver.
An n+1 by n+1 augmented matrix has rank n. (In our simple example n = 2.) The normal (or definite) conductance matrix can be obtained simply by selecting a datum node (e.g. define node 0 to be 0V) and deleting its row and column. The matrix equation GV = I can then be solved for the column vector of voltages ([V1; V2]) by matrix inversion: V = G-1I.
Now here’s the interactive part where we do exactly that:
Look for a future posting on how SPICE deals with time-stepping (’transient analysis’), with reactive, four-terminal, and non-linear elements, and with shorts and voltage sources.
Here’s a link to the web page for the SPICE descendant in Agilent ADS: W2302 Transient Convolution Element
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Happy Birthday little buddy! Glad you were born :>)
Thirty six years indeed! This article makes me feel a little old. But Kirchhoff’s Laws are still valid, and people are still debating branch constituent relations (we also call that modeling).
Thanks, Larry. I’m honored to receive a comment from you!
Great post! Brought back some distant memories for me. I linked to your post from my blog. Looking forward to the rest of the series.
John
NVIDIA GPU Chips Branch Out Into FDTD // Apr 10, 2009 at 7:49 am
[...] So perhaps its not a coincidence that EE Times has published an Viewpoint article Mass GPUs, not CPUs for EDA simulations by my colleague Larry Lerner, R&D senior manager at Agilent Technologies, EEsof EDA division. These accelerator chips, which started life as graphics co-processors, are branching out into EDA, not only for FDTD but also branch constitutive equation evaluation in SPICE circuit simulation. [...]
Thanks for the kind words, John. The next couple of posts will cover shorts, voltages sources, supernodes, reactive components, and four terminal components.
Puzzle Event 3 - Nodal Circuit Simulator // Apr 14, 2009 at 3:10 pm
[...] Circuit Simulation – Part One – SPICE Turns Thirty-Six [...]
Oddly enough, SPICE and I are the same age.
SPICE sims were one of my past times in college. Its nice to see a technology that has maintained its niche.
Circuit Simulation - Part Two - How Various Components and Analyses Are Handled // Apr 20, 2009 at 3:37 pm
[...] Circuit Simulation – Part One – SPICE Turns Thirty-Six [...]
Thank you very much for this presentation. It was really interresting.
Is there a version of Spice that work as library to be used directly inside another program?
A nice tutorial. I remember inverting matrices in school. Thank goodness for computers.
Thanks, Tom. Yes computers will invert a big matrix and then do another and another and another for you with equal enthusiam
Circuit Simulation 2 – How Various Components and Analyses Are Handled // Sep 15, 2009 at 4:00 pm
[...] part one, we just covered DC analysis of conductances and current sources. What about other analyses and [...]